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Diffstat (limited to 'llvm/include/llvm/Target/Target.td')
| -rw-r--r-- | llvm/include/llvm/Target/Target.td | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td index 44ae273f3910..8e93a6e6fd6a 100644 --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -756,6 +756,28 @@ def ins; /// of operands. def variable_ops; +/// variable-length instruction encoding utilities. +/// The `ascend` operator should be used like this: +/// (ascend 0b0000, 0b1111) +/// Which represent a seqence of encoding fragments placing from LSB to MSB. +/// Thus, in this case the final encoding will be 0b11110000. +/// The arguments for `ascend` can either be `bits` or another DAG. +def ascend; +/// In addition, we can use `descend` to describe an encoding that places +/// its arguments (i.e. encoding fragments) from MSB to LSB. For instance: +/// (descend 0b0000, 0b1111) +/// This results in an encoding of 0b00001111. +def descend; +/// The `operand` operator should be used like this: +/// (operand "$src", 4) +/// Which represents a 4-bit encoding for an instruction operand named `$src`. +def operand; +/// Similar to `operand`, we can reference only part of the operand's encoding: +/// (slice "$src", 6, 8) +/// (slice "$src", 8, 6) +/// Both DAG represent bit 6 to 8 (total of 3 bits) in the encoding of operand +/// `$src`. +def slice; /// PointerLikeRegClass - Values that are designed to have pointer width are /// derived from this. TableGen treats the register class as having a symbolic |