diff options
author | Yvan Roux <yvan.roux@linaro.org> | 2021-06-09 15:30:50 +0200 |
---|---|---|
committer | Tom Stellard <tstellar@redhat.com> | 2021-06-15 01:27:12 -0400 |
commit | a95bf588bd727fa71486098d76b8a1bc00650361 (patch) | |
tree | c2dac8112a95d1ed28b5489ed05974130cc8c6c3 | |
parent | a066f4eb679488cfeed2fec24574adcb55f367a1 (diff) |
[ARM] Fix Machine Outliner LDRD/STRD handling in Thumb mode.
This is a fix for PR50481
Immediate values for AddrModeT2_i8s4 are already scaled in MCinst operand.
This patch changes the number of bits and scale factor to reflect that
state when checking stack offset status. AddrModeT2_i7s[2|4] also have
this particularity but since MVE instructions are not outlined, just move
these cases to the unhandled ones.
Differential Revision: https://reviews.llvm.org/D103167
(cherry picked from commit 6c78dbd4ca1f2c25cdc276d646c7920afe856ca3)
-rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 22 | ||||
-rw-r--r-- | llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir | 20 |
2 files changed, 19 insertions, 23 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 112eb59e173d..e418d53b56a4 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -5934,6 +5934,9 @@ bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI, || AddrMode == ARMII::AddrModeT2_so // SP can't be used as based register || AddrMode == ARMII::AddrModeT2_pc // PCrel access || AddrMode == ARMII::AddrMode2 // Used by PRE and POST indexed LD/ST + || AddrMode == ARMII::AddrModeT2_i7 // v8.1-M MVE + || AddrMode == ARMII::AddrModeT2_i7s2 // v8.1-M MVE + || AddrMode == ARMII::AddrModeT2_i7s4 // v8.1-M sys regs VLDR/VSTR || AddrMode == ARMII::AddrModeNone) return false; @@ -5976,6 +5979,10 @@ bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI, NumBits = 8; break; case ARMII::AddrModeT2_i8s4: + // FIXME: Values are already scaled in this addressing mode. + assert((Fixup & 3) == 0 && "Can't encode this offset!"); + NumBits = 10; + break; case ARMII::AddrModeT2_ldrex: NumBits = 8; Scale = 4; @@ -5984,17 +5991,6 @@ bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI, case ARMII::AddrMode_i12: NumBits = 12; break; - case ARMII::AddrModeT2_i7: - NumBits = 7; - break; - case ARMII::AddrModeT2_i7s2: - NumBits = 7; - Scale = 2; - break; - case ARMII::AddrModeT2_i7s4: - NumBits = 7; - Scale = 4; - break; case ARMII::AddrModeT1_s: // SP-relative LD/ST NumBits = 8; Scale = 4; @@ -6004,8 +6000,8 @@ bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI, } // Make sure the offset is encodable for instructions that scale the // immediate. - if (((OffVal * Scale + Fixup) & (Scale - 1)) != 0) - return false; + assert(((OffVal * Scale + Fixup) & (Scale - 1)) == 0 && + "Can't encode this offset!"); OffVal += Fixup / Scale; unsigned Mask = (1 << NumBits) - 1; diff --git a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir index 7d9b19553b08..6c940f15eba6 100644 --- a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir +++ b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir @@ -81,23 +81,23 @@ body: | ;CHECK-LABEL: name: CheckAddrModeT2_i8s4 ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[I8S4:[0-9]+]] - ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 254, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 1020, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14, $noreg tBL 14, $noreg, @foo, implicit-def dead $lr, implicit $sp t2STRDi8 $r0, $r1, $sp, 0, 14, $noreg t2STRDi8 $r0, $r1, $sp, 8, 14, $noreg - t2STRDi8 $r0, $r1, $sp, 253, 14, $noreg - t2STRDi8 $r0, $r1, $sp, 254, 14, $noreg + t2STRDi8 $r0, $r1, $sp, 1012, 14, $noreg + t2STRDi8 $r0, $r1, $sp, 1020, 14, $noreg tBL 14, $noreg, @foo, implicit-def dead $lr, implicit $sp t2STRDi8 $r0, $r1, $sp, 0, 14, $noreg t2STRDi8 $r0, $r1, $sp, 8, 14, $noreg - t2STRDi8 $r0, $r1, $sp, 253, 14, $noreg - t2STRDi8 $r0, $r1, $sp, 254, 14, $noreg + t2STRDi8 $r0, $r1, $sp, 1012, 14, $noreg + t2STRDi8 $r0, $r1, $sp, 1020, 14, $noreg tBL 14, $noreg, @foo, implicit-def dead $lr, implicit $sp t2STRDi8 $r0, $r1, $sp, 0, 14, $noreg t2STRDi8 $r0, $r1, $sp, 8, 14, $noreg - t2STRDi8 $r0, $r1, $sp, 253, 14, $noreg - t2STRDi8 $r0, $r1, $sp, 254, 14, $noreg + t2STRDi8 $r0, $r1, $sp, 1012, 14, $noreg + t2STRDi8 $r0, $r1, $sp, 1020, 14, $noreg BX_RET 14, $noreg ... --- @@ -205,9 +205,9 @@ body: | ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 2, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 10, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 255, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 8, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 16, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRDi8 $r0, $r1, $sp, 1020, 14 /* CC::al */, $noreg ;CHECK-NEXT: $lr, $sp = t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I12]] |