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authorCraig Topper <craig.topper@sifive.com>2022-01-30 14:07:35 -0800
committerCraig Topper <craig.topper@sifive.com>2022-01-30 17:10:34 -0800
commitbb495810d9e3b5029d5a79273c9443ebc9023b7c (patch)
tree527884731a963f0cbbf1a004a14cee665e230c64
parent3931faa59e22e7ce06443cbcf00ef550e5f16dd0 (diff)
[RISCV] Merge rv64zbkb-valid.s and rv64zbkb-only-valid.s. NFC
Based on the existing naming "only" tests are used for rv32 instructions that don't exist in rv64. rv32 tests without "only" are for instructions that are in both rv32 and rv64. The rv64 tests are for instructions that are only in rv64. Both of these test files have instruction encodings that are only valid in rv64 so they can be the same file.
-rw-r--r--llvm/test/MC/RISCV/rv64zbkb-only-valid.s9
-rw-r--r--llvm/test/MC/RISCV/rv64zbkb-valid.s6
2 files changed, 6 insertions, 9 deletions
diff --git a/llvm/test/MC/RISCV/rv64zbkb-only-valid.s b/llvm/test/MC/RISCV/rv64zbkb-only-valid.s
deleted file mode 100644
index 2d3e7381b356..000000000000
--- a/llvm/test/MC/RISCV/rv64zbkb-only-valid.s
+++ /dev/null
@@ -1,9 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkb -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
-# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# CHECK-ASM-AND-OBJ: rev8 t0, t1
-# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
-rev8 t0, t1
diff --git a/llvm/test/MC/RISCV/rv64zbkb-valid.s b/llvm/test/MC/RISCV/rv64zbkb-valid.s
index 01e1f6a760c8..bc3ed8e9246c 100644
--- a/llvm/test/MC/RISCV/rv64zbkb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbkb-valid.s
@@ -1,7 +1,13 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkb -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: rev8 t0, t1
+# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
+rev8 t0, t1
+
# CHECK-ASM-AND-OBJ: rorw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
rorw t0, t1, t2