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authorBenjamin Kramer <benny.kra@googlemail.com>2022-02-12 17:30:06 +0100
committerBenjamin Kramer <benny.kra@googlemail.com>2022-02-12 17:46:12 +0100
commit22e69afa3b1dd9e6c77d3a75a77f6f4094e77a26 (patch)
tree4e8b554e95a0d6db8157a907a24b9d758bbbb352
parent96b7e0b5a0c6bd5742af783ed83cc41c299e9472 (diff)
[MachineRegisterInfo] Simplify code so it matches the description
-rw-r--r--llvm/include/llvm/CodeGen/MachineRegisterInfo.h19
1 files changed, 4 insertions, 15 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 2d34cd6a1660..d3b29081da6f 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -835,23 +835,12 @@ public:
/// to refer to the designated register.
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg,
ArrayRef<MachineInstr *> Users) const {
- SmallSet<MCRegister, 4> OldRegUnits;
- for (MCRegUnitIterator RUI(OldReg, getTargetRegisterInfo()); RUI.isValid();
- ++RUI)
- OldRegUnits.insert(*RUI);
-
// If this operand is a register, check whether it overlaps with OldReg.
// If it does, replace with NewReg.
- auto UpdateOp = [this, &NewReg, &OldReg, &OldRegUnits](MachineOperand &Op) {
- if (Op.isReg()) {
- for (MCRegUnitIterator RUI(OldReg, getTargetRegisterInfo());
- RUI.isValid(); ++RUI) {
- if (OldRegUnits.contains(*RUI)) {
- Op.setReg(NewReg);
- break;
- }
- }
- }
+ auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
+ if (Op.isReg() &&
+ getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg))
+ Op.setReg(NewReg);
};
// Iterate through (possibly several) operands to DBG_VALUEs and update